标签：pac dict ref pipelined 内存 first arc simple ora
Textbook:
《计算机组成与设计——硬件/软件接口》 HI
《计算机体系结构——量化研究方法》 QR
本章要讨论的问题就是 How to Improve Cache Performance?
前面讲过 Average memory access time = HitTime + (MissRate * MissPenalty)
那么我们的方向就是Reduce MissRate / HitTime / MissPenalty
• Reducing hit time
1. Giving Reads Priority over Writes
• E.g., Read complete before earlier writes in write buffer ？？
2. Avoiding Address Translation during Cache Indexing
Cache中使用虚拟地址，这样就可以同时Access TLB和Cache / Access Cache firstly
• Reducing Miss Penalty
3. Multilevel Caches
AMAT = Hit TimeL1 + Miss RateL1 x Miss PenaltyL1
Miss PenaltyL1 = Hit TimeL2 + Miss RateL2 x Miss PenaltyL2
原来Miss PenaltyL1要访问内存，很慢。现在多了L2
• Reducing Miss Rate
4. Larger Block size (Compulsory misses)
...
5. Larger Cache size (Capacity misses)
...
6. Higher Associativity (Conflict misses)
...
• Reducing hit time
1. Small and simple caches（QR P59）
2. Way prediction
3. Trace caches
• Increasing cache bandwidth
4. Pipelined caches
5. Multibanked caches
6. Nonblocking caches
• Reducing Miss Penalty
7. Critical word first
8. Merging write buffers
• Reducing Miss Rate
9. Compiler optimizations
• Reducing miss penalty or miss rate via parallelism
10. Hardware prefetching
11. Compiler prefetching
...
计算机系统结构总结_Memory Hierarchy and Cache Optimization
标签：pac dict ref pipelined 内存 first arc simple ora
原文地址：https://www.cnblogs.com/pdev/p/11621833.html
