标签：|| ctrl inpu other output else define mux tms
1 module mips( 2 input clk, 3 input reset 4 ); 5 6 //output 7 //ctrl_D,E,M,W 8 wire [1:0] RegDst_D,RegDst_E,RegDst_M,RegDst_W; 9 wire RegWrite_D,RegWrite_E,RegWrite_M,RegWrite_W; 10 wire ALUSrc_D,ALUSrc_E,ALUSrc_M,ALUSrc_W; 11 wire MemWrite_D,MemWrite_E,MemWrite_M,MemWrite_W; 12 wire [1:0] MemtoReg_D,MemtoReg_E,MemtoReg_M,MemtoReg_W; 13 wire [1:0] ExtOp_D,ExtOp_E,ExtOp_M,ExtOp_W; 14 wire [3:0] ALUOp_D,ALUOp_E,ALUOp_M,ALUOp_W; 15 wire [2:0] MDUOp_D,MDUOp_E,MDUOp_M,MDUOp_W; 16 wire [3:0] NPCOp_D,NPCOp_E,NPCOp_M,NPCOp_W; 17 //PC 18 wire [31:0] PC_F; 19 //IM 20 wire [31:0] IR_F; 21 //Reg_D 22 wire [31:0] IR_D; 23 wire [31:0] PC_D; 24 //MFRSD 25 wire [31:0] RD1; 26 //MFRTD 27 wire [31:0] RD2; 28 //NPC 29 wire [31:0] NextPC; 30 //GRF 31 wire [31:0] ReadData1; 32 wire [31:0] ReadData2; 33 //EXT 34 wire [31:0] EXTOut; 35 //A3_Mux 36 wire [4:0] WriteReg; 37 //Reg_E 38 wire [31:0] IR_E; 39 wire [31:0] V1_E; 40 wire [31:0] V2_E; 41 wire [4:0] A1_E; 42 wire [4:0] A2_E; 43 wire [4:0] A3_E; 44 wire [31:0] E32_E; 45 wire [31:0] PC_E; 46 //MFRSE 47 wire [31:0] ALU_A; 48 //MFRTE 49 wire [31:0] ALU_B; 50 //ALUSrc 51 wire [31:0] ALU_B_E32; 52 //ALU 53 wire [31:0] ALUOut; 54 //MDU_Ctrl 55 wire Start; 56 wire [1:0] Read; 57 wire Stall_MDU; 58 //MDU 59 wire [31:0] HI; 60 wire [31:0] LO; 61 wire Busy; 62 //ALU_MDU_Out 63 wire [31:0] ALU_MDU_Out; 64 //Reg_M 65 wire [31:0] IR_M; 66 wire [31:0] V2_M; 67 wire [31:0] AMO_M; 68 wire [4:0] A3_M; 69 wire [31:0] PC_M; 70 //RTMsel 71 wire [31:0] WriteData_DM; 72 //BE 73 wire [3:0] BEOp; 74 //DM 75 wire [31:0] ReadData_DM; 76 //Reg_W 77 wire [31:0] IR_W; 78 wire [4:0] A3_W; 79 wire [31:0] PC_W; 80 wire [31:0] AMO_W; 81 wire [31:0] DR_W; 82 //BE_EXT 83 wire [31:0] DMExt; 84 //MemtoReg 85 wire [31:0] WriteData; 86 //Hazards 87 wire Stall; 88 wire [1:0] RSDsel; 89 wire [1:0] RTDsel; 90 wire [1:0] RSEsel; 91 wire [1:0] RTEsel; 92 wire [1:0] RTMsel; 93 //output 94 95 //F级 96 PC PC_P6 ( 97 .Clock(clk), 98 .Reset(reset), 99 .Stop(Stall), 100 .NextPC(NextPC), 101 .PC(PC_F) 102 ); 103 104 IM IM_P6 ( 105 .Address(PC_F[13:2]-12‘hc00), 106 .Instr(IR_F) 107 ); 108 109 Reg_D Reg_D_P6 ( 110 .Clock(clk), 111 .Reset(reset), 112 .Enable(Stall), 113 .IR_F(IR_F), 114 .PC_F(PC_F), 115 .IR_D(IR_D), 116 .NPC_D(PC_D) 117 ); 118 //D级 119 120 //D级 121 ctrl D_ctrl ( 122 .IR(IR_D), 123 .Op(IR_D[31:26]), 124 .Func(IR_D[5:0]), 125 .Rt(IR_D[20:16]), 126 .RegDst(RegDst_D), 127 .RegWrite(RegWrite_D), 128 .ALUSrc(ALUSrc_D), 129 .MemWrite(MemWrite_D), 130 .MemtoReg(MemtoReg_D), 131 .ExtOp(ExtOp_D), 132 .ALUOp(ALUOp_D), 133 .MDUOp(MDUOp_D), 134 .NPCOp(NPCOp_D) 135 ); 136 137 mux_3_32 MFRSD_P6 ( 138 .a(ReadData1), 139 .b(WriteData), 140 .c(AMO_M), 141 .select(RSDsel), 142 .y(RD1) 143 ); 144 145 mux_3_32 MFRTD_P6 ( 146 .a(ReadData2), 147 .b(WriteData), 148 .c(AMO_M), 149 .select(RTDsel), 150 .y(RD2) 151 ); 152 153 NPC NPC_P6 ( 154 .Instr(IR_D[25:0]), 155 .PC_F(PC_F), 156 .PC_D(PC_D), 157 .rs(RD1), 158 .A(RD1), 159 .B(RD2), 160 .NPCOp(NPCOp_D), 161 .npc(NextPC) 162 ); 163 164 GRF GRF_P6 ( 165 .Clock(clk), 166 .Reset(reset), 167 .RegWrite(RegWrite_W), 168 .ReadReg1(IR_D[25:21]), 169 .ReadReg2(IR_D[20:16]), 170 .WriteReg(A3_W), 171 .WriteData(WriteData), 172 .WPC(PC_W), 173 .ReadData1(ReadData1), 174 .ReadData2(ReadData2) 175 ); 176 177 EXT EXT_P6 ( 178 .Imm_16(IR_D[15:0]), 179 .ExtOp(ExtOp_D), 180 .Imm_32(EXTOut) 181 ); 182 183 mux_3_5 A3_Mux_P6 ( 184 .a(IR_D[20:16]), 185 .b(IR_D[15:11]), 186 .c(5‘h1f), 187 .select(RegDst_D), 188 .y(WriteReg) 189 ); 190 191 Reg_E Reg_E_P6 ( 192 .Clock(clk), 193 .Reset(reset | Stall), 194 .IR_D(IR_D), 195 .RF_RD1(RD1), 196 .RF_RD2(RD2), 197 .PC4_D(PC_D), 198 .EXT(EXTOut), 199 .Rs_IR_D(IR_D[25:21]), 200 .Rt_IR_D(IR_D[20:16]), 201 .Rd_IR_D(WriteReg), 202 .IR_E(IR_E), 203 .V1_E(V1_E), 204 .V2_E(V2_E), 205 .A1_E(A1_E), 206 .A2_E(A2_E), 207 .A3_E(A3_E), 208 .E32_E(E32_E), 209 .PC4_E(PC_E) 210 ); 211 //E级 212 213 //E级 214 ctrl E_ctrl ( 215 .IR(IR_E), 216 .Op(IR_E[31:26]), 217 .Func(IR_E[5:0]), 218 .Rt(IR_E[20:16]), 219 .RegDst(RegDst_E), 220 .RegWrite(RegWrite_E), 221 .ALUSrc(ALUSrc_E), 222 .MemWrite(MemWrite_E), 223 .MemtoReg(MemtoReg_E), 224 .ExtOp(ExtOp_E), 225 .ALUOp(ALUOp_E), 226 .MDUOp(MDUOp_E), 227 .NPCOp(NPCOp_E) 228 ); 229 230 mux_3_32 MFRSE_P6 ( 231 .a(V1_E), 232 .b(WriteData), 233 .c(AMO_M), 234 .select(RSEsel), 235 .y(ALU_A) 236 ); 237 238 mux_3_32 MFRTE_P6 ( 239 .a(V2_E), 240 .b(WriteData), 241 .c(AMO_M), 242 .select(RTEsel), 243 .y(ALU_B) 244 ); 245 246 assign ALU_B_E32 = (ALUSrc_E == 0) ? ALU_B : E32_E; 247 248 ALU ALU_P6 ( 249 .A(ALU_A), 250 .B(ALU_B_E32), 251 .s(IR_E[10:6]), 252 .ALUOp(ALUOp_E), 253 .Result(ALUOut) 254 ); 255 256 MDU_Ctrl MDU_Ctrl_P6 ( 257 .IR_D(IR_D), 258 .IR_E(IR_E), 259 .Busy(Busy), 260 .Start(Start), 261 .Read(Read), 262 .Stall_MDU(Stall_MDU) 263 ); 264 265 MDU MDU_P6 ( 266 .Clock(clk), 267 .Reset(reset), 268 .Start(Start), 269 .A(ALU_A), 270 .B(ALU_B_E32), 271 .MDUOp(MDUOp_E), 272 .HI(HI), 273 .LO(LO), 274 .Busy(Busy) 275 ); 276 277 assign ALU_MDU_Out = (Read == 1) ? HI : 278 (Read == 2) ? LO : 279 ALUOut; 280 281 Reg_M Reg_M_P6 ( 282 .Clock(clk), 283 .Reset(reset), 284 .ALU_MDU_Out(ALU_MDU_Out), 285 .ALU_B(ALU_B), 286 .IR_E(IR_E), 287 .PC4_E(PC_E), 288 .A3_E(A3_E), 289 .IR_M(IR_M), 290 .V2_M(V2_M), 291 .AMO_M(AMO_M), 292 .A3_M(A3_M), 293 .PC4_M(PC_M) 294 ); 295 //M级 296 297 //M级 298 ctrl M_ctrl ( 299 .IR(IR_M), 300 .Op(IR_M[31:26]), 301 .Func(IR_M[5:0]), 302 .Rt(IR_M[20:16]), 303 .RegDst(RegDst_M), 304 .RegWrite(RegWrite_M), 305 .ALUSrc(ALUSrc_M), 306 .MemWrite(MemWrite_M), 307 .MemtoReg(MemtoReg_M), 308 .ExtOp(ExtOp_M), 309 .ALUOp(ALUOp_M), 310 .MDUOp(MDUOp_M), 311 .NPCOp(NPCOp_M) 312 ); 313 314 BE BE_P6 ( 315 .Op(IR_M[31:26]), 316 .Addr(AMO_M[1:0]), 317 .BEOp(BEOp) 318 ); 319 320 assign WriteData_DM = (RTMsel == 1) ? WriteData : V2_M; 321 322 DM DM_P6 ( 323 .Clock(clk), 324 .Reset(reset), 325 .MemWrite(MemWrite_M), 326 .BE(BEOp), 327 .WriteData(WriteData_DM), 328 .pc(PC_M), 329 .addr(AMO_M), 330 .ReadData(ReadData_DM) 331 ); 332 333 Reg_W Reg_W_P6 ( 334 .Clock(clk), 335 .Reset(reset), 336 .IR_M(IR_M), 337 .A3_M(A3_M), 338 .AMO_M(AMO_M), 339 .PC4_M(PC_M), 340 .DMOut(ReadData_DM), 341 .IR_W(IR_W), 342 .A3_W(A3_W), 343 .PC4_W(PC_W), 344 .AMO_W(AMO_W), 345 .DR_W(DR_W) 346 ); 347 //W级 348 349 //W级 350 ctrl W_ctrl ( 351 .IR(IR_W), 352 .Op(IR_W[31:26]), 353 .Func(IR_W[5:0]), 354 .Rt(IR_W[20:16]), 355 .RegDst(RegDst_W), 356 .RegWrite(RegWrite_W), 357 .ALUSrc(ALUSrc_W), 358 .MemWrite(MemWrite_W), 359 .MemtoReg(MemtoReg_W), 360 .ExtOp(ExtOp_W), 361 .ALUOp(ALUOp_W), 362 .MDUOp(MDUOp_W), 363 .NPCOp(NPCOp_W) 364 ); 365 366 BE_EXT BE_EXT_P6 ( 367 .DMOut(DR_W), 368 .Addr(AMO_W[1:0]), 369 .Op(IR_W[31:26]), 370 .DMExt(DMExt) 371 ); 372 373 mux_3_32 MemtoReg_Mux_P6 ( 374 .a(AMO_W), 375 .b(DMExt), 376 .c(PC_W+8), 377 .select(MemtoReg_W), 378 .y(WriteData) 379 ); 380 //W级 381 382 //Hazards 383 Hazards Hazards_P6 ( 384 .IR_D(IR_D), 385 .IR_E(IR_E), 386 .IR_M(IR_M), 387 .IR_W(IR_W), 388 .A3_E(A3_E), 389 .A3_M(A3_M), 390 .A3_W(A3_W), 391 .W_E(RegWrite_E), 392 .W_M(RegWrite_M), 393 .W_W(RegWrite_W), 394 .Stall_MDU(Stall_MDU), 395 .Stall(Stall), 396 .RSDsel(RSDsel), 397 .RTDsel(RTDsel), 398 .RSEsel(RSEsel), 399 .RTEsel(RTEsel), 400 .RTMsel(RTMsel) 401 ); 402 //Hazards 403 404 endmodule
1 module PC( 2 input Clock, 3 input Reset, 4 input Stop, 5 input [31:0] NextPC, 6 output reg [31:0] PC 7 ); 8 9 initial begin 10 PC = 32‘h0000_3000; 11 end 12 13 always @ (posedge Clock) begin 14 if(Reset == 1) 15 PC = 32‘h0000_3000; 16 else if(Stop == 1) 17 PC = PC; 18 else 19 PC = NextPC; 20 end 21 22 endmodule
1 module IM( 2 input [11:0] Address, 3 output [31:0] Instr 4 ); 5 6 reg [31:0] memory [4095:0]; 7 integer i; 8 9 initial begin 10 for(i = 0; i < 4095; i = i + 1) 11 memory[i] = 32‘h0; 12 $readmemh("code.txt",memory); 13 end 14 15 assign Instr = memory[Address]; 16 17 endmodule
1 module Reg_D( 2 input Clock, 3 input Reset, 4 input Enable, 5 input [31:0] IR_F, 6 input [31:0] PC_F, 7 output reg [31:0] IR_D, 8 output reg [31:0] NPC_D 9 ); 10 11 initial begin 12 IR_D = 0; 13 NPC_D = 0; 14 end 15 16 always @ (posedge Clock) begin 17 if(Reset == 1) begin 18 IR_D <= 0; 19 NPC_D <= 0; 20 end 21 else if(Enable == 1) begin 22 IR_D <= IR_D; 23 NPC_D <= NPC_D; 24 end 25 else begin 26 IR_D <= IR_F; 27 NPC_D <= PC_F; 28 end 29 end 30 31 endmodule
1 module ctrl( 2 input [31:0] IR, 3 input [5:0] Op, 4 input [5:0] Func, 5 input [4:0] Rt, 6 output [1:0] RegDst, 7 output RegWrite, 8 output ALUSrc, 9 output MemWrite, 10 output [1:0] MemtoReg, 11 output [1:0] ExtOp, 12 output [3:0] ALUOp, 13 output [2:0] MDUOp, 14 output [3:0] NPCOp 15 ); 16 17 reg LB,LBU,LH,LHU,LW, 18 SB,SH,SW, 19 ADD,ADDU,SUB,SUBU, 20 MULT,MULTU,DIV,DIVU, 21 SLL,SRL,SRA,SLLV,SRLV,SRAV, 22 AND,OR,XOR,NOR, 23 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 24 SLT,SLTI,SLTIU,SLTU, 25 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 26 J,JAL,JALR,JR, 27 MFHI,MFLO,MTHI,MTLO; 28 29 initial begin 30 {LB,LBU,LH,LHU,LW,SB,SH,SW, 31 ADD,ADDU,SUB,SUBU, 32 MULT,MULTU,DIV,DIVU, 33 SLL,SRL,SRA,SLLV,SRLV,SRAV, 34 AND,OR,XOR,NOR, 35 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 36 SLT,SLTI,SLTIU,SLTU, 37 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 38 J,JAL,JALR,JR, 39 MFHI,MFLO,MTHI,MTLO} = 42‘b0; 40 end 41 42 assign RegDst = (ADD | ADDU | AND | NOR | OR | SUB | SUBU | XOR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | MFHI | MFLO | JALR) ? 2‘b01 : 43 (JAL) ? 2‘b10 : 44 2‘b00; 45 46 assign RegWrite = (ADD | ADDU | AND | NOR | OR | SUB | SUBU | XOR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | ADDI | ADDIU | ANDI | ORI | XORI | SLTI | SLTIU | LUI | MFHI | MFLO | JAL | JALR | LB | LBU | LH | LHU | LW) ? 1 : 47 0; 48 49 assign ALUSrc = (ADDI | ADDIU | ANDI | ORI | XORI | SLTI | SLTIU | LUI | LB | LBU | LH | LHU | LW | SB | SH | SW) ? 1 : 50 0; 51 52 assign MemWrite = (SB | SH | SW) ? 1 : 53 0; 54 55 assign MemtoReg = (LB | LBU | LH | LHU | LW) ? 2‘b01 : 56 (JAL | JALR) ? 2‘b10 : 57 2‘b00; 58 59 assign ExtOp = (ANDI | ORI | XORI) ? 2‘b01 : 60 (LUI) ? 2‘b10 : 61 2‘b00; 62 63 assign ALUOp = (AND | ANDI) ? 4‘b0001 : 64 (NOR) ? 4‘b0010 : 65 (OR | ORI) ? 4‘b0011 : 66 (SUB | SUBU) ? 4‘b0100 : 67 (XOR | XORI) ? 4‘b0101 : 68 (SLL) ? 4‘b0110 : 69 (SLLV) ? 4‘b0111 : 70 (SLT | SLTI) ? 4‘b1000 : 71 (SLTU | SLTIU) ? 4‘b1001 : 72 (SRA) ? 4‘b1010 : 73 (SRAV) ? 4‘b1011 : 74 (SRL) ? 4‘b1100 : 75 (SRLV) ? 4‘b1101 : 76 4‘b0000; 77 78 assign MDUOp = (DIVU) ? 3‘b001 : 79 (MULT) ? 3‘b010 : 80 (MULTU)? 3‘b011 : 81 (MTHI) ? 3‘b100 : 82 (MTLO) ? 3‘b101 : 83 3‘b000; 84 85 86 87 assign NPCOp = (BEQ) ? 4‘b0001 : 88 (BGEZ) ? 4‘b0010 : 89 (BGTZ) ? 4‘b0011 : 90 (BLEZ) ? 4‘b0100 : 91 (BLTZ) ? 4‘b0101 : 92 (BNE) ? 4‘b0110 : 93 (J | JAL) ? 4‘b0111 : 94 (JALR | JR) ? 4‘b1000 : 95 4‘b0000; 96 97 always @ (IR or Op or Func or Rt) begin 98 {LB,LBU,LH,LHU,LW,SB,SH,SW, 99 ADD,ADDU,SUB,SUBU, 100 MULT,MULTU,DIV,DIVU, 101 SLL,SRL,SRA,SLLV,SRLV,SRAV, 102 AND,OR,XOR,NOR, 103 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 104 SLT,SLTI,SLTIU,SLTU, 105 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 106 J,JAL,JALR,JR, 107 MFHI,MFLO,MTHI,MTLO} = 42‘b0; 108 case(Op) 109 6‘b000000: begin 110 case(Func) 111 6‘b000000: SLL = 1; 112 6‘b000010: SRL = 1; 113 6‘b000011: SRA = 1; 114 6‘b000100: SLLV = 1; 115 6‘b000110: SRLV = 1; 116 6‘b000111: SRAV = 1; 117 6‘b001000: JR = 1; 118 6‘b001001: JALR = 1; 119 6‘b010000: MFHI = 1; 120 6‘b010001: MTHI = 1; 121 6‘b010010: MFLO = 1; 122 6‘b010011: MTLO = 1; 123 6‘b011000: MULT = 1; 124 6‘b011001: MULTU = 1; 125 6‘b011010: DIV = 1; 126 6‘b011011: DIVU = 1; 127 6‘b100000: ADD = 1; 128 6‘b100001: ADDU = 1; 129 6‘b100010: SUB = 1; 130 6‘b100011: SUBU = 1; 131 6‘b100100: AND = 1; 132 6‘b100101: OR = 1; 133 6‘b100110: XOR = 1; 134 6‘b100111: NOR = 1; 135 6‘b101010: SLT = 1; 136 6‘b101011: SLTU = 1; 137 endcase 138 end 139 6‘b000001: begin 140 case(Rt) 141 5‘b00000: BLTZ = 1; 142 5‘b00001: BGEZ = 1; 143 endcase 144 end 145 6‘b000010: J = 1; 146 6‘b000011: JAL = 1; 147 6‘b000100: BEQ = 1; 148 6‘b000101: BNE = 1; 149 6‘b000110: BLEZ = 1; 150 6‘b000111: BGTZ = 1; 151 6‘b001000: ADDI = 1; 152 6‘b001001: ADDIU = 1; 153 6‘b001010: SLTI = 1; 154 6‘b001011: SLTIU = 1; 155 6‘b001100: ANDI = 1; 156 6‘b001101: ORI = 1; 157 6‘b001110: XORI = 1; 158 6‘b001111: LUI = 1; 159 6‘b100000: LB = 1; 160 6‘b100001: LH = 1; 161 6‘b100011: LW = 1; 162 6‘b100100: LBU = 1; 163 6‘b100101: LHU = 1; 164 6‘b101000: SB = 1; 165 6‘b101001: SH = 1; 166 6‘b101011: SW = 1; 167 default: {LB,LBU,LH,LHU,LW,SB,SH,SW, 168 ADD,ADDU,SUB,SUBU, 169 MULT,MULTU,DIV,DIVU, 170 SLL,SRL,SRA,SLLV,SRLV,SRAV, 171 AND,OR,XOR,NOR, 172 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 173 SLT,SLTI,SLTIU,SLTU, 174 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 175 J,JAL,JALR,JR, 176 MFHI,MFLO,MTHI,MTLO} = 42‘b0; 177 endcase 178 end 179 endmodule
1 module NPC( 2 input [25:0] Instr, 3 input [31:0] PC_F, 4 input [31:0] PC_D, 5 input [31:0] rs, 6 input [31:0] A, 7 input [31:0] B, 8 input [3:0] NPCOp, 9 output [31:0] npc 10 ); 11 12 wire [15:0] offset; 13 wire [31:0] PC_F4; 14 wire [31:0] PC_D4; 15 parameter OTHER = 4‘b0000, 16 BEQ = 4‘b0001, 17 BGEZ = 4‘b0010, 18 BGTZ = 4‘b0011, 19 BLEZ = 4‘b0100, 20 BLTZ = 4‘b0101, 21 BNE = 4‘b0110, 22 J_JAL = 4‘b0111, 23 JALR_JR=4‘b1000; 24 25 assign offset = Instr[15:0]; 26 27 assign PC_F4 = PC_F + 4; 28 assign PC_D4 = PC_D + 4; 29 30 assign npc = (NPCOp == OTHER) ? PC_F4 : 31 ((NPCOp == BEQ) & (A == B)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 32 ((NPCOp == BGEZ) & ($signed(A) >= 0)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 33 ((NPCOp == BGTZ) & ($signed(A) > 0)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 34 ((NPCOp == BLEZ) & ($signed(A) <= 0)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 35 ((NPCOp == BLTZ) & ($signed(A) < 0)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 36 ((NPCOp == BNE) & (A != B)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 37 (NPCOp == J_JAL) ? {PC_D[31:28],Instr,2‘b00} : 38 (NPCOp == JALR_JR) ? rs : 39 PC_D4 + 4; 40 41 endmodule
1 module GRF( 2 input Clock, 3 input Reset, 4 input RegWrite, 5 input [4:0] ReadReg1, 6 input [4:0] ReadReg2, 7 input [4:0] WriteReg, 8 input [31:0] WriteData, 9 input [31:0] WPC, 10 output [31:0] ReadData1, 11 output [31:0] ReadData2 12 ); 13 14 reg [31:0] register[31:0]; 15 integer i; 16 17 initial begin 18 for(i = 0; i < 32; i = i + 1) 19 register[i] = 32‘b0; 20 end 21 22 assign ReadData1 = (ReadReg1 == WriteReg && WriteReg != 0 && RegWrite == 1) ? WriteData : register[ReadReg1]; 23 assign ReadData2 = (ReadReg2 == WriteReg && WriteReg != 0 && RegWrite == 1) ? WriteData : register[ReadReg2]; 24 25 always @ (posedge Clock) begin 26 if(Reset == 1) 27 for(i = 0; i < 32; i = i + 1) 28 register[i] = 32‘b0; 29 else if(RegWrite == 1 && WriteReg != 0) begin 30 register[WriteReg] = WriteData; 31 $display("%d@%h: $%d <= %h", $time, WPC, WriteReg,WriteData); 32 end 33 end 34 35 endmodule
1 module EXT( 2 input [15:0] Imm_16, 3 input [1:0] ExtOp, 4 output [31:0] Imm_32 5 ); 6 7 parameter sign = 2‘b00, 8 zero = 2‘b01, 9 high = 2‘b10, 10 sign_left_2 = 2‘b11; 11 12 assign Imm_32 = (ExtOp == sign) ? {{16{Imm_16[15]}},Imm_16} : 13 (ExtOp == zero) ? {{16‘b0}, Imm_16} : 14 (ExtOp == high) ? {Imm_16,{16‘b0}} : 15 {{14{Imm_16[15]}},Imm_16,2‘b00}; 16 17 endmodule
1 module Reg_E( 2 input Clock, 3 input Reset, 4 input [31:0] IR_D, 5 input [31:0] RF_RD1, 6 input [31:0] RF_RD2, 7 input [31:0] PC4_D, 8 input [31:0] EXT, 9 input [4:0] Rs_IR_D, 10 input [4:0] Rt_IR_D, 11 input [4:0] Rd_IR_D, 12 output reg [31:0] IR_E, 13 output reg [31:0] V1_E, 14 output reg [31:0] V2_E, 15 output reg [4:0] A1_E, 16 output reg [4:0] A2_E, 17 output reg [4:0] A3_E, 18 output reg [31:0] E32_E, 19 output reg [31:0] PC4_E 20 ); 21 22 initial begin 23 IR_E = 0; 24 V1_E = 0; 25 V2_E = 0; 26 A1_E = 0; 27 A2_E = 0; 28 A3_E = 0; 29 E32_E = 0; 30 PC4_E = 32‘h0000_3000; 31 end 32 33 always @ (posedge Clock) begin 34 if(Reset == 1) begin 35 IR_E <= 0; 36 V1_E <= 0; 37 V2_E <= 0; 38 A1_E <= 0; 39 A2_E <= 0; 40 A3_E <= 0; 41 E32_E <= 0; 42 PC4_E <= 32‘h0000_3000; 43 end 44 else begin 45 IR_E <= IR_D; 46 V1_E <= RF_RD1; 47 V2_E <= RF_RD2; 48 A1_E <= Rs_IR_D; 49 A2_E <= Rt_IR_D; 50 A3_E <= Rd_IR_D; 51 E32_E <= EXT; 52 PC4_E <= PC4_D; 53 end 54 end 55 56 endmodule
1 module ALU( 2 input [31:0] A, 3 input [31:0] B, 4 input [4:0] s, 5 input [3:0] ALUOp, 6 output [31:0] Result 7 ); 8 9 parameter ADD = 4‘b0000, 10 AND = 4‘b0001, 11 NOR = 4‘b0010, 12 OR = 4‘b0011, 13 SUB = 4‘b0100, 14 XOR = 4‘b0101, 15 SLL = 4‘b0110, 16 SLLV = 4‘b0111, 17 SLT = 4‘b1000, 18 SLTU = 4‘b1001, 19 SRA = 4‘b1010, 20 SRAV = 4‘b1011, 21 SRL = 4‘b1100, 22 SRLV = 4‘b1101; 23 24 assign Result = (ALUOp == ADD) ? (A + B) : 25 (ALUOp == AND) ? (A & B) : 26 (ALUOp == NOR) ? ~(A | B) : 27 (ALUOp == OR) ? (A | B) : 28 (ALUOp == SUB) ? (A - B) : 29 (ALUOp == XOR) ? (A ^ B) : 30 (ALUOp == SLL) ? (B << s) : 31 (ALUOp == SLLV)? (B << A[4:0]) : 32 (ALUOp == SLT) ? ($signed(A) < $signed(B)) : 33 (ALUOp == SLTU)? ({1‘b0,A} < {1‘b0,B}) : 34 (ALUOp == SRA) ? $signed($signed(B) >>> s) : 35 (ALUOp == SRAV)? $signed($signed(B) >>> A[4:0]) : 36 (ALUOp == SRL) ? (B >> s) : 37 (ALUOp == SRLV)? (B >> A[4:0]) : 38 0; 39 40 endmodule
1 module MDU_Ctrl( 2 input [31:0] IR_D, 3 input [31:0] IR_E, 4 input Busy, 5 output Start, 6 output [1:0] Read, 7 output Stall_MDU 8 ); 9 10 wire [5:0] Op_D,Op_E; 11 wire [5:0] Func_D,Func_E; 12 13 assign Op_D = IR_D[31:26]; 14 assign Func_D = IR_D[5:0]; 15 assign Op_E = IR_E[31:26]; 16 assign Func_E = IR_E[5:0]; 17 18 assign Start = (Busy==0) & (Op_E==0) & (Func_E>=6‘b010000 && Func_E<=6‘b011011 && Func_E!=6‘b010000 && Func_E!=6‘b010010); 19 assign Read = (Busy==0) & (Op_E==0) & (Func_E==6‘b010000) ? 2‘b01 : 20 (Busy==0) & (Op_E==0) & (Func_E==6‘b010010) ? 2‘b10 : 21 2‘b00; 22 assign Stall_MDU = (Busy==1 || Start==1) & (Op_D==0) & (Func_D>=6‘b010000 && Func_D<=6‘b011011); 23 24 25 endmodule
1 module MDU( 2 input Clock, 3 input Reset, 4 input Start, 5 input [31:0] A, 6 input [31:0] B, 7 input [2:0] MDUOp, 8 output reg [31:0] HI, 9 output reg [31:0] LO, 10 output Busy 11 ); 12 13 integer delay; 14 parameter DIV = 3‘b000, 15 DIVU = 3‘b001, 16 MULT = 3‘b010, 17 MULTU= 3‘b011, 18 MTHI = 3‘b100, 19 MTLO = 3‘b101; 20 21 initial begin 22 HI = 0; 23 LO = 0; 24 delay = 0; 25 end 26 27 always @(posedge Clock) begin 28 if(Reset == 1) begin 29 HI = 0; 30 LO = 0; 31 delay = 0; 32 end 33 else if(Start==1 && delay==0) begin 34 case(MDUOp) 35 DIV: begin 36 HI = $signed(A) % $signed(B); 37 LO = $signed(A) / $signed(B); 38 delay = 10; 39 end 40 DIVU: begin 41 HI = A % B; 42 LO = A / B; 43 delay = 10; 44 end 45 MULT: begin 46 {HI,LO} = $signed(A) * $signed(B); 47 delay = 5; 48 end 49 MULTU:begin 50 {HI,LO} = A * B; 51 delay = 5; 52 end 53 MTHI: begin 54 HI = A; 55 delay = 0; 56 end 57 MTLO: begin 58 LO = A; 59 delay = 0; 60 end 61 default: delay = 0; 62 endcase 63 end 64 if(delay != 0) 65 delay = delay - 1; 66 end 67 68 assign Busy = (delay != 0); 69 70 endmodule
1 module Reg_M( 2 input Clock, 3 input Reset, 4 input [31:0] ALU_MDU_Out, 5 input [31:0] ALU_B, 6 input [31:0] IR_E, 7 input [31:0] PC4_E, 8 input [4:0] A3_E, 9 output reg [31:0] IR_M, 10 output reg [31:0] V2_M, 11 output reg [31:0] AMO_M, 12 output reg [4:0] A3_M, 13 output reg [31:0] PC4_M 14 ); 15 16 initial begin 17 IR_M = 0; 18 V2_M = 0; 19 AMO_M = 0; 20 A3_M = 0; 21 PC4_M = 32‘h0000_3000; 22 end 23 24 always @ (posedge Clock) begin 25 if(Reset == 1) begin 26 IR_M <= 0; 27 V2_M <= 0; 28 AMO_M <= 0; 29 A3_M <= 0; 30 PC4_M <= 32‘h0000_3000; 31 end 32 else begin 33 IR_M <= IR_E; 34 V2_M <= ALU_B; 35 AMO_M <= ALU_MDU_Out; 36 A3_M <= A3_E; 37 PC4_M <= PC4_E; 38 end 39 end 40 41 endmodule
1 module BE( 2 input [5:0] Op, 3 input [1:0] Addr, 4 output [3:0] BEOp 5 ); 6 7 parameter sb = 6‘b101000, 8 sh = 6‘b101001, 9 sw = 6‘b101011; 10 11 assign BEOp = ((Op == sb) & (Addr == 2‘b00)) ? 4‘b0001 : 12 ((Op == sb) & (Addr == 2‘b01)) ? 4‘b0010 : 13 ((Op == sb) & (Addr == 2‘b10)) ? 4‘b0100 : 14 ((Op == sb) & (Addr == 2‘b11)) ? 4‘b1000 : 15 ((Op == sh) & (Addr[1] == 1‘b0)) ? 4‘b0011 : 16 ((Op == sh) & (Addr[1] == 1‘b1)) ? 4‘b1100 : 17 4‘b1111; 18 endmodule
1 module DM( 2 input Clock, 3 input Reset, 4 input MemWrite, 5 input [3:0] BE, 6 input [31:0] WriteData, 7 input [31:0] pc, 8 input [31:0] addr, 9 output[31:0] ReadData 10 ); 11 12 reg [31:0] memory[4095:0]; 13 wire [11:0] A; 14 wire [31:0] AExt; 15 integer i; 16 17 initial begin 18 for(i = 0; i < 4095; i = i + 1) 19 memory[i] = 32‘h0; 20 end 21 22 assign A = addr[13:2]; 23 assign AExt = {18‘b0,A,2‘b0}; 24 25 assign ReadData = memory[A]; 26 27 always @ (posedge Clock) begin 28 if(Reset == 1) 29 for(i = 0; i < 4095; i = i + 1) 30 memory[i] = 32‘h0; 31 else if(MemWrite == 1) begin 32 case(BE) 33 4‘b0001: begin 34 memory[A][7:0] = WriteData[7:0]; 35 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 36 end 37 4‘b0010: begin 38 memory[A][15:8] = WriteData[7:0]; 39 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 40 end 41 4‘b0100: begin 42 memory[A][23:16] = WriteData[7:0]; 43 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 44 end 45 4‘b1000: begin 46 memory[A][31:24] = WriteData[7:0]; 47 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 48 end 49 50 4‘b0011: begin 51 memory[A][15:0] = WriteData[15:0]; 52 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 53 end 54 4‘b1100: begin 55 memory[A][31:16] = WriteData[15:0]; 56 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 57 end 58 59 4‘b1111: begin 60 memory[A] = WriteData; 61 $display("%d@%h: *%h <= %h", $time, pc, AExt,memory[A]); 62 end 63 endcase 64 end 65 end 66 67 endmodule
1 module Reg_W( 2 input Clock, 3 input Reset, 4 input [31:0] IR_M, 5 input [4:0] A3_M, 6 input [31:0] AMO_M, 7 input [31:0] PC4_M, 8 input [31:0] DMOut, 9 output reg [31:0] IR_W, 10 output reg [4:0] A3_W, 11 output reg [31:0] PC4_W, 12 output reg [31:0] AMO_W, 13 output reg [31:0] DR_W 14 ); 15 16 initial begin 17 IR_W = 0; 18 A3_W = 0; 19 PC4_W = 32‘h0000_3000; 20 AMO_W = 0; 21 DR_W = 0; 22 end 23 24 always @ (posedge Clock) begin 25 if(Reset == 1) begin 26 IR_W <= 0; 27 A3_W <= 0; 28 PC4_W <= 32‘h0000_3000; 29 AMO_W <= 0; 30 DR_W <= 0; 31 end 32 else begin 33 IR_W <= IR_M; 34 A3_W <= A3_M; 35 PC4_W <= PC4_M; 36 AMO_W <= AMO_M; 37 DR_W <= DMOut; 38 end 39 end 40 41 endmodule
1 module BE_EXT( 2 input [31:0] DMOut, 3 input [1:0] Addr, 4 input [5:0] Op, 5 output [31:0] DMExt 6 ); 7 8 parameter lb = 6‘b100000, 9 lbu = 6‘b100100, 10 lh = 6‘b100001, 11 lhu = 6‘b100101, 12 lw = 6‘b100011; 13 14 assign DMExt = ((Op == lb ) & (Addr == 2‘b00)) ? {{24{DMOut[7]}},DMOut[7:0]} : 15 ((Op == lb ) & (Addr == 2‘b01)) ? {{24{DMOut[15]}},DMOut[15:8]} : 16 ((Op == lb ) & (Addr == 2‘b10)) ? {{24{DMOut[23]}},DMOut[23:16]} : 17 ((Op == lb ) & (Addr == 2‘b11)) ? {{24{DMOut[31]}},DMOut[31:24]} : 18 ((Op == lbu) & (Addr == 2‘b00)) ? {{24‘b0},DMOut[7:0]} : 19 ((Op == lbu) & (Addr == 2‘b01)) ? {{24‘b0},DMOut[15:8]} : 20 ((Op == lbu) & (Addr == 2‘b10)) ? {{24‘b0},DMOut[23:16]} : 21 ((Op == lbu) & (Addr == 2‘b11)) ? {{24‘b0},DMOut[31:24]} : 22 ((Op == lh ) & (Addr == 2‘b00)) ? {{16{DMOut[15]}},DMOut[15:0]} : 23 ((Op == lh ) & (Addr == 2‘b10)) ? {{16{DMOut[31]}},DMOut[31:16]} : 24 ((Op == lhu) & (Addr == 2‘b00)) ? {{16‘b0},DMOut[15:0]} : 25 ((Op == lhu) & (Addr == 2‘b10)) ? {{16‘b0},DMOut[31:16]} : 26 DMOut; 27 28 endmodule
1 `define rs 25:21 2 `define rt 20:16 3 module Hazards( 4 input [31:0] IR_D, 5 input [31:0] IR_E, 6 input [31:0] IR_M, 7 input [31:0] IR_W, 8 input [4:0] A3_E, 9 input [4:0] A3_M, 10 input [4:0] A3_W, 11 input W_E, 12 input W_M, 13 input W_W, 14 input Stall_MDU, 15 output Stall, 16 output [1:0] RSDsel, 17 output [1:0] RTDsel, 18 output [1:0] RSEsel, 19 output [1:0] RTEsel, 20 output [1:0] RTMsel 21 ); 22 23 wire Stall_RS0_EA,Stall_RS0_ED,Stall_RS0_MD,Stall_RS1_ED; 24 wire Stall_RT0_EA,Stall_RT0_ED,Stall_RT0_MD,Stall_RT1_ED; 25 26 wire [1:0] Tnew_E,Tnew_M,Tnew_W; 27 wire [1:0] Tuse_RS,Tuse_RT; 28 29 assign Stall_RS0_EA = (Tuse_RS == 0) & (Tnew_E == 1) & (IR_D[`rs] == A3_E) & (IR_D[`rs] != 0) & W_E; 30 assign Stall_RS0_ED = (Tuse_RS == 0) & (Tnew_E == 2) & (IR_D[`rs] == A3_E) & (IR_D[`rs] != 0) & W_E; 31 assign Stall_RS0_MD = (Tuse_RS == 0) & (Tnew_M == 1) & (IR_D[`rs] == A3_M) & (IR_D[`rs] != 0) & W_M; 32 assign Stall_RS1_ED = (Tuse_RS == 1) & (Tnew_E == 2) & (IR_D[`rs] == A3_E) & (IR_D[`rs] != 0) & W_E; 33 34 assign Stall_RT0_EA = (Tuse_RT == 0) & (Tnew_E == 1) & (IR_D[`rt] == A3_E) & (IR_D[`rt] != 0) & W_E; 35 assign Stall_RT0_ED = (Tuse_RT == 0) & (Tnew_E == 2) & (IR_D[`rt] == A3_E) & (IR_D[`rt] != 0) & W_E; 36 assign Stall_RT0_MD = (Tuse_RT == 0) & (Tnew_M == 1) & (IR_D[`rt] == A3_M) & (IR_D[`rt] != 0) & W_M; 37 assign Stall_RT1_ED = (Tuse_RT == 1) & (Tnew_E == 2) & (IR_D[`rt] == A3_E) & (IR_D[`rt] != 0) & W_E; 38 39 assign Stall = Stall_RS0_EA | Stall_RS0_ED | Stall_RS0_MD | Stall_RS1_ED | 40 Stall_RT0_EA | Stall_RT0_ED | Stall_RT0_MD | Stall_RT1_ED | 41 Stall_MDU; 42 43 assign RSDsel = ( (IR_D[`rs]==A3_M) & (IR_D[`rs]!=0) & (Tnew_M==0) & W_M ) ? 2 : 44 ( (IR_D[`rs]==A3_W) & (IR_D[`rs]!=0) & W_W ) ? 1 : 45 0; 46 47 assign RTDsel = ( (IR_D[`rt]==A3_M) & (IR_D[`rt]!=0) & (Tnew_M==0) & W_M ) ? 2 : 48 ( (IR_D[`rt]==A3_W) & (IR_D[`rt]!=0) & W_W ) ? 1 : 49 0; 50 51 assign RSEsel = ( (IR_E[`rs]==A3_M) & (IR_E[`rs]!=0) & (Tnew_M==0) & W_M ) ? 2 : 52 ( (IR_E[`rs]==A3_W) & (IR_E[`rs]!=0) & W_W ) ? 1 : 53 0; 54 55 assign RTEsel = ( (IR_E[`rt]==A3_M) & (IR_E[`rt]!=0) & (Tnew_M==0) & W_M ) ? 2 : 56 ( (IR_E[`rt]==A3_W) & (IR_E[`rt]!=0) & W_W ) ? 1 : 57 0; 58 59 assign RTMsel = ( (IR_M[`rt]==A3_W) & (IR_M[`rt]!=0) & W_W ) ? 1 : 0; 60 61 ControlHazards T_USE ( 62 .IR(IR_D), 63 .Tuse_rs(Tuse_RS), 64 .Tuse_rt(Tuse_RT) 65 ); 66 67 ControlHazards T_E ( 68 .IR(IR_E), 69 .TnewSrc(2‘b00), 70 .Tnew(Tnew_E) 71 ); 72 73 ControlHazards T_M ( 74 .IR(IR_M), 75 .TnewSrc(2‘b01), 76 .Tnew(Tnew_M) 77 ); 78 79 ControlHazards T_W ( 80 .IR(IR_W), 81 .TnewSrc(2‘b10), 82 .Tnew(Tnew_W) 83 ); 84 85 86 87 endmodule
1 module ControlHazards( 2 input [31:0] IR, 3 input [1:0] TnewSrc, 4 output [1:0] Tuse_rs, 5 output [1:0] Tuse_rt, 6 output [1:0] Tnew 7 ); 8 9 wire [5:0] Op; 10 wire [5:0] Func; 11 wire [4:0] Rt; 12 wire cal_r,cal_i,MF,MT,MD,load,store,branch,j,jr,jal,jalr; 13 wire [1:0] Tnew_E,Tnew_M,Tnew_W; 14 15 reg LB,LBU,LH,LHU,LW, 16 SB,SH,SW, 17 ADD,ADDU,SUB,SUBU, 18 MULT,MULTU,DIV,DIVU, 19 SLL,SRL,SRA,SLLV,SRLV,SRAV, 20 AND,OR,XOR,NOR, 21 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 22 SLT,SLTI,SLTIU,SLTU, 23 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 24 J,JAL,JALR,JR, 25 MFHI,MFLO,MTHI,MTLO; 26 27 initial begin 28 {LB,LBU,LH,LHU,LW,SB,SH,SW, 29 ADD,ADDU,SUB,SUBU, 30 MULT,MULTU,DIV,DIVU, 31 SLL,SRL,SRA,SLLV,SRLV,SRAV, 32 AND,OR,XOR,NOR, 33 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 34 SLT,SLTI,SLTIU,SLTU, 35 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 36 J,JAL,JALR,JR, 37 MFHI,MFLO,MTHI,MTLO} = 0; 38 end 39 40 assign Op = IR[31:26]; 41 assign Func = IR[5:0]; 42 assign Rt = IR[20:16]; 43 44 always @ (IR or Op or Func or Rt) begin 45 {LB,LBU,LH,LHU,LW,SB,SH,SW, 46 ADD,ADDU,SUB,SUBU, 47 MULT,MULTU,DIV,DIVU, 48 SLL,SRL,SRA,SLLV,SRLV,SRAV, 49 AND,OR,XOR,NOR, 50 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 51 SLT,SLTI,SLTIU,SLTU, 52 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 53 J,JAL,JALR,JR, 54 MFHI,MFLO,MTHI,MTLO} = 42‘b0; 55 case(Op) 56 6‘b000000: begin 57 case(Func) 58 6‘b000000: SLL = 1; 59 6‘b000010: SRL = 1; 60 6‘b000011: SRA = 1; 61 6‘b000100: SLLV = 1; 62 6‘b000110: SRLV = 1; 63 6‘b000111: SRAV = 1; 64 6‘b001000: JR = 1; 65 6‘b001001: JALR = 1; 66 6‘b010000: MFHI = 1; 67 6‘b010001: MTHI = 1; 68 6‘b010010: MFLO = 1; 69 6‘b010011: MTLO = 1; 70 6‘b011000: MULT = 1; 71 6‘b011001: MULTU = 1; 72 6‘b011010: DIV = 1; 73 6‘b011011: DIVU = 1; 74 6‘b100000: ADD = 1; 75 6‘b100001: ADDU = 1; 76 6‘b100010: SUB = 1; 77 6‘b100011: SUBU = 1; 78 6‘b100100: AND = 1; 79 6‘b100101: OR = 1; 80 6‘b100110: XOR = 1; 81 6‘b100111: NOR = 1; 82 6‘b101010: SLT = 1; 83 6‘b101011: SLTU = 1; 84 endcase 85 end 86 6‘b000001: begin 87 case(Rt) 88 5‘b00000: BLTZ = 1; 89 5‘b00001: BGEZ = 1; 90 endcase 91 end 92 6‘b000010: J = 1; 93 6‘b000011: JAL = 1; 94 6‘b000100: BEQ = 1; 95 6‘b000101: BNE = 1; 96 6‘b000110: BLEZ = 1; 97 6‘b000111: BGTZ = 1; 98 6‘b001000: ADDI = 1; 99 6‘b001001: ADDIU = 1; 100 6‘b001010: SLTI = 1; 101 6‘b001011: SLTIU = 1; 102 6‘b001100: ANDI = 1; 103 6‘b001101: ORI = 1; 104 6‘b001110: XORI = 1; 105 6‘b001111: LUI = 1; 106 6‘b100000: LB = 1; 107 6‘b100001: LH = 1; 108 6‘b100011: LW = 1; 109 6‘b100100: LBU = 1; 110 6‘b100101: LHU = 1; 111 6‘b101000: SB = 1; 112 6‘b101001: SH = 1; 113 6‘b101011: SW = 1; 114 default: {LB,LBU,LH,LHU,LW,SB,SH,SW, 115 ADD,ADDU,SUB,SUBU, 116 MULT,MULTU,DIV,DIVU, 117 SLL,SRL,SRA,SLLV,SRLV,SRAV, 118 AND,OR,XOR,NOR, 119 ADDI,ADDIU,ANDI,ORI,XORI,LUI, 120 SLT,SLTI,SLTIU,SLTU, 121 BEQ,BNE,BLEZ,BGTZ,BLTZ,BGEZ, 122 J,JAL,JALR,JR, 123 MFHI,MFLO,MTHI,MTLO} = 42‘b0; 124 endcase 125 end 126 127 assign cal_r = ADD | ADDU | AND | NOR | OR | SUB | SUBU | XOR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV; 128 assign cal_i = ADDI | ADDIU | ANDI | ORI | XORI | SLTI | SLTIU | LUI; 129 assign MF = MFHI | MFLO; 130 assign MT = MTHI | MTLO; 131 assign MD = MULT | MULTU | DIV | DIVU; 132 assign load = LB | LBU | LH | LHU | LW; 133 assign store = SB | SH | SW; 134 assign branch = BEQ | BGEZ | BGTZ | BLEZ | BLTZ | BNE; 135 assign j = J; 136 assign jr = JR; 137 assign jal = JAL; 138 assign jalr = JALR; 139 140 assign Tnew_E = (cal_r | cal_i | MF) ? 2‘b01 : 141 2‘b10; 142 assign Tnew_M = (cal_r | cal_i | MF) ? 2‘b00 : 143 2‘b01; 144 assign Tnew_W = (cal_r | cal_i | MF) ? 2‘b00 : 145 2‘b00; 146 147 assign Tuse_rs = (branch | jr | jalr) ? 2‘b00 : 148 (cal_r | cal_i | MT | MD | load | store) ? 2‘b01 : 149 2‘b11; 150 151 assign Tuse_rt = (branch) ? 2‘b00 : 152 (cal_r | MD) ? 2‘b01 : 153 (store) ? 2‘b10 : 154 2‘b11; 155 156 assign Tnew = (TnewSrc == 2‘b00 ) ? Tnew_E : 157 (TnewSrc == 2‘b01 ) ? Tnew_M : 158 Tnew_W; 159 endmodule
1 module mux_3_5( 2 input [4:0] a,b,c, 3 input [1:0] select, 4 output [4:0] y 5 ); 6 7 assign y = (select == 2) ? c : 8 (select == 1) ? b : 9 a; 10 endmodule 11 12 module mux_3_32( 13 input [31:0] a,b,c, 14 input [1:0] select, 15 output [31:0] y 16 ); 17 18 assign y = (select == 2) ? c : 19 (select == 1) ? b : 20 a; 21 endmodule
标签：|| ctrl inpu other output else define mux tms
原文地址：https://www.cnblogs.com/tuoniao/p/10203198.html
