VIVADO(1)

标签：font   design   共享   verilog   info   span   bit   数据库   style   

VIVADO 流程：

 input：verilog/VHDL/System Verilog             /IP/DSP/uP;

synthesis：synth_design、report_timing_summary;

implementation：opt_design、place_design、route_design、report_timing_summary;

generate bit 。

---------------------------------------------------------------------------------------------------------

synth_design :3rd party EDIF、XDC;

---------------------------------------------------------------------------------------------------------

synth_design、opt_design、place_design、route_design =======>Design Checkpoint (.dcp);

        ||                    ||                      ||                               ||

    top.dcp          top_opt.dcp    top_placed.dcp  top_routed.dcp

Design Checkpoint include：EDIF、XDC、XDEF;

---------------------------------------------------------------------------------------------------------

VIVADO 以IP为核心设计：

IP Catalog

 --------------------------------------------------------------------------------------------------------------------------------

VIVADO 共享数据库（.dcp）     

---------------------------------------------------------------------------------------------------------------------------------

VIVADO(1)

标签：font   design   共享   verilog   info   span   bit   数据库   style   

原文地址：https://www.cnblogs.com/alke-95/p/13040558.html