QAM调制---Verilog代码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/05/28 11:41:08
// Design Name: 
// Module Name: DATA_16QAM_mapper
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


//原书提供的代码是有问题的！！！


module DATA_16QAM_mapper(

    input               wire                   DM_CLK,
    input               wire                   DM_RST,
    input               wire                   DM_DIN,
    input               wire                   DM_ND,
    output              reg       [7:0]        DM_RE,
    output              reg       [7:0]        DM_IM,
    output              reg       [5:0]        DM_INDEX,
    output              reg                    DM_RDY

    );

//----------------------------------------------------------------------

reg[3:0] STOR;
reg[1:0] counter;
reg      MAPEN;
reg      OUTEN;
reg[7:0] RE_TEMP;    
reg[7:0] IM_TEMP;
reg[5:0] DM_COUNT;
reg      OUTEN;
reg[1:0] OUT_COUNT;


always @(negedge DM_RST or posedge DM_CLK)
begin
    if(!DM_RST)
    begin
        MAPEN<=1‘b0;
        STOR[3:0] <= 4‘b0000;
        counter[1:0] <= 2‘b00;
        RE_TEMP[7:0]<=8‘b00000000;
        IM_TEMP[7:0]<=8‘b00000000;
        OUTEN<=0;
        DM_RE[7:0]<=8‘b00000000;
        DM_IM[7:0]<=8‘b00000000;
        DM_COUNT[5:0]<=6‘b000000;
        DM_INDEX[5:0]<=6‘b000000;
        DM_RDY<=0;
        OUT_COUNT<=2‘b00;

    end
    else 
    begin
        if(DM_ND)
        begin
            counter<=counter+1;
            case(counter)
                2‘b00:STOR[0]<=DM_DIN;
                2‘b01:STOR[1]<=DM_DIN;           //存入输入数值
                2‘b10:STOR[2]<=DM_DIN;
                2‘b11:STOR[3]<=DM_DIN;
           endcase
        end
        else 
        begin
            counter <=2‘b00; 
              STOR  <=4‘b0000;
        end

        if (counter==2‘b11)       // MAPEN 标记四个信号是否已经存入
            MAPEN<=1‘b1;
        else
            MAPEN<=1‘b0;

        if(MAPEN)
        begin
               case(STOR[1:0])
                2‘b00:RE_TEMP[7:0]<=8‘b11000011;
                2‘b10:RE_TEMP[7:0]<=8‘b11101100;
                2‘b01:RE_TEMP[7:0]<=8‘b00111101;
                2‘b11:RE_TEMP[7:0]<=8‘b00010100; 
               endcase
            case(STOR[3:2])
                2‘b00:IM_TEMP[7:0]<=8‘b11000011;
                2‘b10:IM_TEMP[7:0]<=8‘b11101100;
                2‘b01:IM_TEMP[7:0]<=8‘b00111101;
                2‘b11:IM_TEMP[7:0]<=8‘b00010100;
            endcase
            OUTEN<=1;
        end
        else
        begin
            OUTEN<=0;
            RE_TEMP[7:0]<=8‘b00000000;
            IM_TEMP[7:0]<=8‘b00000000;
        end

        if(OUTEN)
        begin
           DM_RE<=RE_TEMP;
              DM_IM<=IM_TEMP;

              if(DM_COUNT==47)
                      DM_COUNT<=0;
           else
                   DM_COUNT<=DM_COUNT+1;

           DM_INDEX<=DM_COUNT;
           DM_RDY<=1‘b1;
        end

        if (DM_INDEX==47)
           OUT_COUNT<=OUT_COUNT+1;

        if (OUT_COUNT==2‘b11)
        begin
           DM_RE[7:0]<=8‘b00000000;
           DM_IM[7:0]<=8‘b00000000;
           DM_INDEX[5:0]<=6‘b000000;
           DM_COUNT[5:0]<=6‘b000000;
           DM_RDY<=0;
        end
    end
end

endmodule