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Understanding the STM32F0‘s GPIO

This is the first part of the GPIO tutorial for the STM32F0Discovery.

The tutorial will include the following topics:

• Understanding the Structure of the GPIO Registers on the STM32F0 Microcontroller
• Understanding how to access the registers
• Setting and clearing output pins

The STM32F051 microcontroller on the STM32F0Discovery board

has 5 general purpose input/output (GPIO) ports named Port A, B, C, D and F.

Each port can have up to 16 pins, and each port has associated with it the following set of registers:

• GPIO port mode register (GPIOx_MODER)
• GPIO port output type register (GPIOx_OTYPER)
• GPIO port output speed register (GPIOx_OSPEEDR)
• GPIO port pull-up/pull-down register (GPIOx_PUPDR)
• GPIO port input data register (GPIOx _IDR)
• GPIO port outp ut data register (GPIOx_ODR)
• GPIO port bit set/reset register (GPIOx _BSRR)
• GPIO port configuration lock register (GPIOx_LCKR)
• GPIO alternate function low register (GPI Ox_AFRL)
• GPIO alternate function high register (GPIOx_AFRH)
• GPIO Port bit reset register (GPIOx_BRR)

where the ‘x‘ in each register name acronym represents the port i.e.

the GPIOx_MODER associated with port A is called GPIOA_MODER.

Let‘s take a closer look at each register:

GPIO port mode register (GPIOx_MODER)

This is a 32-bit register where each set of two consecutive bits represent the mode of a single I/O pin.

For example bits 0 and 1  of the MODER register associated with GPIOC (GPIOC_MODER),

represent the mode of GPIO pin PC0 and bits 26 and 27 of the same register represent the mode of GPIO pin PC13.

These two bits can be set to:

• ‘00‘-> input mode, which allows the GPIO pin to be used as an input pin,
• ‘01‘-> Output mode, which allows the GPIO pin to be used as an output pin,
• ‘11‘-> Analog mode, which allows the GPIO pin to be used as an Analog input pin and finally,
• ‘10‘-> Alternate function mode which allow the GPIO pins to be used by peripherals such as the UART, SPI e.t.c.
  It is important to note that if a pin‘s MODE is set to alternate function, 
  any GPIO settings for that pin in the GPIO registers will be overridden by the peripheral.

This is a 16-bit register where each bit denotes the ‘type‘ of a single pin in the register.

This register sets the type of output pins to either push-pull or open drain.

For example if pin PC7 is configured as an output pin,

clearing bit 7 (or leaving its state at zero) of the OTYPER register associated with GPIOC (GPIOC_TYPER),

will set the output type of the GPIO output pin PC7 to "Push-Pull".

GPIO port output speed register (GPIOx_OSPEEDR)

This is a 32-bit register where each set of two bits represent the speed of a single output pin.

For example bits 0 and 1  of the OSPEEDR register associated with port C (GPIOC_OSPEEDR),

represent the speed setting of the output pin PC0 and bits 26 and 27 of the same register

represent the speed setting of the output pin PC13. These two bits can be set to:

• ‘x0‘: 2MHz Low speed
• ‘01‘:10MHz Medium speed
• ‘11‘: 50MHz High speed

So why have a speed setting on I/O ?

To save power. 

On the 2MHz setting the GPIO would consume less current than on the 50MHz setting

I‘d imagine but would have relatively longer rise/fall time specs.

The User Manual for the STM32F0 claims that the the output pins fastest toggle speed is every two clock cycles.

Assuming a maximum operation speed of 48MHz, the fastest toggle speed for the GPIO on the STM32f0 is 24 MHZ,

which means the highest frequency square wave that can be produced by the GPIO is 12MHz.

NOTE:

A quick look at the default startup code found in"system_stm32f0xx.c"

will identify that the  microcontroller is indeed operating at a maximum speed of 48MHz at startup.

In a future entry I will demonstrate how this speed can be changed.

GPIO port pull-up/pull-down register (GPIOx_PUPDR)

The GPIOx_PUPDR registers configures the internal pull-ups and pull-down resistors on each I/O pin.

The internal pull-up/down resistors can be configured on GPIO pins set as input or output

(though I‘d imagine they‘d be more popular on input pins).

The Pullup/down resistors have a typical value of 40KOhms but can range from 30-50Kohms.

Again each two consecutive bits represent the internal pull-up/down resistor setting for each pin within a single port.

GPIO port input data register (GPIOx _IDR)

This is a 16-bit read-only register. Each bit represents the input value on a corresponding pin.

Reading a ‘0‘ in bit 8 of this GPIOC _IDR register indicates that the voltage on PC8 is 0V (GND).

While reading a ‘1‘ in bit 8 of this GPIOC _IDR register indicates that the voltage on PC8 is 3.3V (VDD)

GPIO port output data register (GPIOx_ODR)

This is a 16-bit read/write register. Each bit represents the output value on a corresponding pin.

Writing a ‘0‘ in bit 8 of this GPIOC _ODR register indicates that the voltage on PC8 is driven by the micro to 0V (GND).

While writing a ‘1‘ in bit 8 of this GPIOC _ODR register indicates that the voltage on PC8 is driven by the micro to 3.3V (VDD).

Writing to the ODR register is good  if you want to write to the entire port.e.g.

GPIOC->ODR = 0xF0FE

The above statement changes the state of every pin on the GPIOC peripheral from its previous (and now discarded)  state,

to the one indicated by the statement; 0xF0FE  (0b1111000011111110).

However if you want to set only a single pin;

lets say PC8 without affecting  the state of the rest of the pins on GPIOC,

you have to perform a read-modify-write (RMW) access.

To set pin PC8  independent of all other pins on GPIOC (RMW) you could use:

GPIOC->ODR |=  0x00000100;  //( 0b00000000000000000000000100000000)

To clear pin PC8 independent of all other pins on GPIOC (RMW) you could use:

GPIOC->ODR &=  ~(0x00000100);  //( 0b00000000000000000000000100000000)

This works just fine, but you have to read the ODR register,

OR (|) or AND(&) (modify) it with a mask

and then write it back to the ODR register.

This means that at the assembly language level, at least three instructions

are used to set/clear an I/O which can significantly slow down toggling speed.

A better way would be to use the BSRR register  and the BRR registers for setting and clearing pins.

They enable ‘atomic‘ access that allows the I/O pin to be clear/set in as short a time as possible.

GPIO port bit set/reset register (GPIOx _BSRR)

Note: If both BSx and BRx are set, BSx has priority.

As mentioned in the preceding paragraph the BSRR register allows us to set/clear a particular pin (or groups of pins)

while preserving the state of the rest of the pins on a GPIO peripheral atomically

i.e. a fast as possible, without having to resort to the slower read-modify-write (RMW) accesses.

The least significant 16 bits are used to atomically set pin values to VDD

whereas the most significant 16 bits are used to atomically clear pin values to GND.

So if I wanted to set PC8 independent of all other pins on GPIOC I could use:

GPIOC->BSRR = 0x00000100;//( 0b00000000000000000000000100000000)

or

GPIOC->BSRR = (1<<8);

To clear pin PC8 independent of all other pins on GPIOC you could use:

GPIOC->BSRR = 0x01000000; //( 0b00000001000000000000000000000000)

or

GPIOC->BSRR = (1<<24);

Notice how in both scenarios a simple assignment operator ‘=‘ (atomic)

was used rather than an ‘|=‘ or an ‘&=‘ which denote RMW accesses.

Furthermore, note that to clear the pin value of PC8 to GND,

I had to set the 24th bit in the BSRR (8th bit of the most significant 16 bits).

While to  set the pin value of PC8 to VDD, I had to set the 8th bit in the BSRR.

The awkwardness of atomic clearing being mapped to the most significant 16-bits of the BSRR register

is compensated for by the inclusion of the BRR register.

The BRR register maps the  most significant 16-bits of the BSRR register into itself.

So to clear pin PC8 independent of all other pins on GPIOC you could use:

GPIOC->BRR = (1<<8);

Finally there are three more registers;

the GPIOx_AFRH, GPIOx_AFRL, and the GPIOx_LCKR registers.

The first two allow GPIO pins to be used for alternate functions.

There is a really neat pin muxing mechanism that allows each GPIO to be mapped

to multiple alternate functions depending on how these two registers are set.

I will spend more time on the AFRL/AFRH registers in future entries.

The last GPIOx_LCKR register can be used once GPIO

is configured to ‘lock‘ the configuration so that it does not change until the micro is reset.

I encourage you to look up these three registers in the user manual.

Understanding the STM32F0's GPIO

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原文地址：http://www.cnblogs.com/shangdawei/p/4723915.html