标签:c log mat matlab ca ase
VERILOG:
case(a)
1‘b0:
begin
end
1‘b1:
endcase
if()
else
MATLAB:
switch(a),case(1),b=1;case(2),b=2;otherwise,b=3;end
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原文地址:http://www.cnblogs.com/southernduck/p/3856377.html